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Espressif Systems /ESP32-S3 /SPI0 /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TOTAL_TRANS_END_INT_ST)TOTAL_TRANS_END_INT_ST 0 (ECC_ERR_INT_ST)ECC_ERR_INT_ST

Description

SPI1 interrupt status register

Fields

TOTAL_TRANS_END_INT_ST

The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.
ECC_ERR_INT_ST

The status bit for SPI_MEM_ECC_ERR_INT interrupt.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data